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<div class="header">
  <div class="headertitle"><div class="title">Peripheral_registers_structures <div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a></div></div></div>
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<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-nested-classes" class="groupheader"><a id="nested-classes" name="nested-classes"></a>
Classes</h2></td></tr>
<tr class="memitem:ADC_5FTypeDef" id="r_ADC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_a_d_c___type_def.html">ADC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analog to Digital Converter.  <a href="struct_a_d_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:ADC_5FCommon_5FTypeDef" id="r_ADC_5FCommon_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_a_d_c___common___type_def.html">ADC_Common_TypeDef</a></td></tr>
<tr class="memitem:VREFBUF_5FTypeDef" id="r_VREFBUF_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_v_r_e_f_b_u_f___type_def.html">VREFBUF_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">VREFBUF.  <a href="struct_v_r_e_f_b_u_f___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FDCAN_5FGlobalTypeDef" id="r_FDCAN_5FGlobalTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_d_c_a_n___global_type_def.html">FDCAN_GlobalTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">FD Controller Area Network.  <a href="struct_f_d_c_a_n___global_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TTCAN_5FTypeDef" id="r_TTCAN_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_t_c_a_n___type_def.html">TTCAN_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TTFD Controller Area Network.  <a href="struct_t_t_c_a_n___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FDCAN_5FClockCalibrationUnit_5FTypeDef" id="r_FDCAN_5FClockCalibrationUnit_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_d_c_a_n___clock_calibration_unit___type_def.html">FDCAN_ClockCalibrationUnit_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">FD Controller Area Network.  <a href="struct_f_d_c_a_n___clock_calibration_unit___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:CEC_5FTypeDef" id="r_CEC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_e_c___type_def.html">CEC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Consumer Electronics Control.  <a href="struct_c_e_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:CORDIC_5FTypeDef" id="r_CORDIC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_o_r_d_i_c___type_def.html">CORDIC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">COordincate Rotation DIgital Computer.  <a href="struct_c_o_r_d_i_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:CRC_5FTypeDef" id="r_CRC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_r_c___type_def.html">CRC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">CRC calculation unit.  <a href="struct_c_r_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:CRS_5FTypeDef" id="r_CRS_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_r_s___type_def.html">CRS_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Recovery System.  <a href="struct_c_r_s___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DAC_5FTypeDef" id="r_DAC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_a_c___type_def.html">DAC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Digital to Analog Converter.  <a href="struct_d_a_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DFSDM_5FFilter_5FTypeDef" id="r_DFSDM_5FFilter_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_f_s_d_m___filter___type_def.html">DFSDM_Filter_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">DFSDM module registers.  <a href="struct_d_f_s_d_m___filter___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DFSDM_5FChannel_5FTypeDef" id="r_DFSDM_5FChannel_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_f_s_d_m___channel___type_def.html">DFSDM_Channel_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">DFSDM channel configuration registers.  <a href="struct_d_f_s_d_m___channel___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DBGMCU_5FTypeDef" id="r_DBGMCU_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_b_g_m_c_u___type_def.html">DBGMCU_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Debug MCU.  <a href="struct_d_b_g_m_c_u___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DCMI_5FTypeDef" id="r_DCMI_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_c_m_i___type_def.html">DCMI_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCMI.  <a href="struct_d_c_m_i___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:PSSI_5FTypeDef" id="r_PSSI_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_p_s_s_i___type_def.html">PSSI_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">PSSI.  <a href="struct_p_s_s_i___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DMA_5FStream_5FTypeDef" id="r_DMA_5FStream_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Controller.  <a href="struct_d_m_a___stream___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DMA_5FTypeDef" id="r_DMA_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a___type_def.html">DMA_TypeDef</a></td></tr>
<tr class="memitem:BDMA_5FChannel_5FTypeDef" id="r_BDMA_5FChannel_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_b_d_m_a___channel___type_def.html">BDMA_Channel_TypeDef</a></td></tr>
<tr class="memitem:BDMA_5FTypeDef" id="r_BDMA_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_b_d_m_a___type_def.html">BDMA_TypeDef</a></td></tr>
<tr class="memitem:DMAMUX_5FChannel_5FTypeDef" id="r_DMAMUX_5FChannel_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a_m_u_x___channel___type_def.html">DMAMUX_Channel_TypeDef</a></td></tr>
<tr class="memitem:DMAMUX_5FChannelStatus_5FTypeDef" id="r_DMAMUX_5FChannelStatus_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a_m_u_x___channel_status___type_def.html">DMAMUX_ChannelStatus_TypeDef</a></td></tr>
<tr class="memitem:DMAMUX_5FRequestGen_5FTypeDef" id="r_DMAMUX_5FRequestGen_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a_m_u_x___request_gen___type_def.html">DMAMUX_RequestGen_TypeDef</a></td></tr>
<tr class="memitem:DMAMUX_5FRequestGenStatus_5FTypeDef" id="r_DMAMUX_5FRequestGenStatus_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a_m_u_x___request_gen_status___type_def.html">DMAMUX_RequestGenStatus_TypeDef</a></td></tr>
<tr class="memitem:MDMA_5FTypeDef" id="r_MDMA_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_d_m_a___type_def.html">MDMA_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">MDMA Controller.  <a href="struct_m_d_m_a___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:MDMA_5FChannel_5FTypeDef" id="r_MDMA_5FChannel_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_d_m_a___channel___type_def.html">MDMA_Channel_TypeDef</a></td></tr>
<tr class="memitem:DMA2D_5FTypeDef" id="r_DMA2D_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_m_a2_d___type_def.html">DMA2D_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA2D Controller.  <a href="struct_d_m_a2_d___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:ETH_5FTypeDef" id="r_ETH_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_t_h___type_def.html">ETH_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ethernet MAC.  <a href="struct_e_t_h___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:EXTI_5FTypeDef" id="r_EXTI_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_x_t_i___type_def.html">EXTI_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">External Interrupt/Event Controller.  <a href="struct_e_x_t_i___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:EXTI_5FCore_5FTypeDef" id="r_EXTI_5FCore_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_x_t_i___core___type_def.html">EXTI_Core_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only.  <a href="struct_e_x_t_i___core___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FLASH_5FTypeDef" id="r_FLASH_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_l_a_s_h___type_def.html">FLASH_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">FLASH Registers.  <a href="struct_f_l_a_s_h___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FMAC_5FTypeDef" id="r_FMAC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_m_a_c___type_def.html">FMAC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Filter and Mathematical ACcelerator.  <a href="struct_f_m_a_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FMC_5FBank1_5FTypeDef" id="r_FMC_5FBank1_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_m_c___bank1___type_def.html">FMC_Bank1_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flexible Memory Controller.  <a href="struct_f_m_c___bank1___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FMC_5FBank1E_5FTypeDef" id="r_FMC_5FBank1E_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_m_c___bank1_e___type_def.html">FMC_Bank1E_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flexible Memory Controller Bank1E.  <a href="struct_f_m_c___bank1_e___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FMC_5FBank2_5FTypeDef" id="r_FMC_5FBank2_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_m_c___bank2___type_def.html">FMC_Bank2_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flexible Memory Controller Bank2.  <a href="struct_f_m_c___bank2___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FMC_5FBank3_5FTypeDef" id="r_FMC_5FBank3_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_m_c___bank3___type_def.html">FMC_Bank3_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flexible Memory Controller Bank3.  <a href="struct_f_m_c___bank3___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:FMC_5FBank5_5F6_5FTypeDef" id="r_FMC_5FBank5_5F6_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_m_c___bank5__6___type_def.html">FMC_Bank5_6_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flexible Memory Controller Bank5 and 6.  <a href="struct_f_m_c___bank5__6___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:GPIO_5FTypeDef" id="r_GPIO_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">General Purpose I/O.  <a href="struct_g_p_i_o___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:OPAMP_5FTypeDef" id="r_OPAMP_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_o_p_a_m_p___type_def.html">OPAMP_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Operational Amplifier (OPAMP)  <a href="struct_o_p_a_m_p___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:SYSCFG_5FTypeDef" id="r_SYSCFG_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_y_s_c_f_g___type_def.html">SYSCFG_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">System configuration controller.  <a href="struct_s_y_s_c_f_g___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:I2C_5FTypeDef" id="r_I2C_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i2_c___type_def.html">I2C_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Inter-integrated Circuit Interface.  <a href="struct_i2_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:IWDG_5FTypeDef" id="r_IWDG_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_i_w_d_g___type_def.html">IWDG_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Independent WATCHDOG.  <a href="struct_i_w_d_g___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:LTDC_5FTypeDef" id="r_LTDC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_l_t_d_c___type_def.html">LTDC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">LCD-TFT Display Controller.  <a href="struct_l_t_d_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:LTDC_5FLayer_5FTypeDef" id="r_LTDC_5FLayer_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_l_t_d_c___layer___type_def.html">LTDC_Layer_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">LCD-TFT Display layer x Controller.  <a href="struct_l_t_d_c___layer___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:PWR_5FTypeDef" id="r_PWR_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_p_w_r___type_def.html">PWR_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Power Control.  <a href="struct_p_w_r___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:RCC_5FTypeDef" id="r_RCC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_c_c___type_def.html">RCC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset and Clock Control.  <a href="struct_r_c_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:RTC_5FTypeDef" id="r_RTC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_t_c___type_def.html">RTC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Real-Time Clock.  <a href="struct_r_t_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:SAI_5FTypeDef" id="r_SAI_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_a_i___type_def.html">SAI_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Serial Audio Interface.  <a href="struct_s_a_i___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:SAI_5FBlock_5FTypeDef" id="r_SAI_5FBlock_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_a_i___block___type_def.html">SAI_Block_TypeDef</a></td></tr>
<tr class="memitem:SPDIFRX_5FTypeDef" id="r_SPDIFRX_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_p_d_i_f_r_x___type_def.html">SPDIFRX_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPDIF-RX Interface.  <a href="struct_s_p_d_i_f_r_x___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:SDMMC_5FTypeDef" id="r_SDMMC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_d_m_m_c___type_def.html">SDMMC_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure digital input/output Interface.  <a href="struct_s_d_m_m_c___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DLYB_5FTypeDef" id="r_DLYB_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_l_y_b___type_def.html">DLYB_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Block DLYB.  <a href="struct_d_l_y_b___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:HSEM_5FTypeDef" id="r_HSEM_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_h_s_e_m___type_def.html">HSEM_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">HW Semaphore HSEM.  <a href="struct_h_s_e_m___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:HSEM_5FCommon_5FTypeDef" id="r_HSEM_5FCommon_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_h_s_e_m___common___type_def.html">HSEM_Common_TypeDef</a></td></tr>
<tr class="memitem:SPI_5FTypeDef" id="r_SPI_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_p_i___type_def.html">SPI_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Serial Peripheral Interface.  <a href="struct_s_p_i___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:DTS_5FTypeDef" id="r_DTS_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_t_s___type_def.html">DTS_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">DTS.  <a href="struct_d_t_s___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:TIM_5FTypeDef" id="r_TIM_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_i_m___type_def.html">TIM_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">TIM.  <a href="struct_t_i_m___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:LPTIM_5FTypeDef" id="r_LPTIM_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_l_p_t_i_m___type_def.html">LPTIM_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">LPTIMIMER.  <a href="struct_l_p_t_i_m___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:COMPOPT_5FTypeDef" id="r_COMPOPT_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_o_m_p_o_p_t___type_def.html">COMPOPT_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Comparator.  <a href="struct_c_o_m_p_o_p_t___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:COMP_5FTypeDef" id="r_COMP_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_o_m_p___type_def.html">COMP_TypeDef</a></td></tr>
<tr class="memitem:COMP_5FCommon_5FTypeDef" id="r_COMP_5FCommon_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_o_m_p___common___type_def.html">COMP_Common_TypeDef</a></td></tr>
<tr class="memitem:USART_5FTypeDef" id="r_USART_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Universal Synchronous Asynchronous Receiver Transmitter.  <a href="struct_u_s_a_r_t___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:SWPMI_5FTypeDef" id="r_SWPMI_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_w_p_m_i___type_def.html">SWPMI_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Single Wire Protocol Master Interface SPWMI.  <a href="struct_s_w_p_m_i___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:WWDG_5FTypeDef" id="r_WWDG_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_w_w_d_g___type_def.html">WWDG_TypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Window WATCHDOG.  <a href="struct_w_w_d_g___type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:RAMECC_5FMonitorTypeDef" id="r_RAMECC_5FMonitorTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_a_m_e_c_c___monitor_type_def.html">RAMECC_MonitorTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">RAM_ECC_Specific_Registers.  <a href="struct_r_a_m_e_c_c___monitor_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:RAMECC_5FTypeDef" id="r_RAMECC_5FTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_a_m_e_c_c___type_def.html">RAMECC_TypeDef</a></td></tr>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
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